{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1552825613817 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1552825613827 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 17 20:26:53 2019 " "Processing started: Sun Mar 17 20:26:53 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1552825613827 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1552825613827 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off exp030 -c exp030 --gen_testbench " "Command: quartus_eda --read_settings_files=on --write_settings_files=off exp030 -c exp030 --gen_testbench" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1552825613827 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "exp030 5CSXFC6D6F31C6 " "Selected device 5CSXFC6D6F31C6 for design \"exp030\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1552825615398 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1552825615698 ""}
{ "Info" "ITBO_DONE_VT_GENERATION" "E:/My_design/exp030/simulation/modelsim/exp030.vt " "Generated Verilog Test Bench File E:/My_design/exp030/simulation/modelsim/exp030.vt for simulation" {  } {  } 0 201000 "Generated Verilog Test Bench File %1!s! for simulation" 0 0 "EDA Netlist Writer" 0 -1 1552825615700 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4719 " "Peak virtual memory: 4719 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1552825615928 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 17 20:26:55 2019 " "Processing ended: Sun Mar 17 20:26:55 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1552825615928 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1552825615928 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1552825615928 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1552825615928 ""}